lead Design Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Job Description: Lead Design Engineer – UCIe Verification
Location: Bangalore, India
Function: Design Verification
Role: Lead Design Engineer – UCIe Controller Verification
Role Overview
We are looking for a highly motivated and technically strong Lead Design Engineer – Verification to join our UCIe verification team in Bangalore.
The candidate will contribute to the verification of complex UCIe Controller IP , working on next-generation chiplet and die-to-die interconnect solutions. The role requires strong hands-on expertise in SystemVerilog/UVM , verification architecture, coverage-driven verification, protocol verification, and debug.
The engineer will work closely with design, architecture, validation, and other cross-functional teams to develop scalable verification environments, validate complex protocol scenarios, drive coverage closure, debug failures, and contribute toward high-quality IP releases.

Required Qualifications

- BE/BTech/ME/MTech/MS in Electronics, Electrical Engineering, Computer Engineering, or a related discipline.

- 5+ years of relevant Design Verification experience , with strong hands-on ownership of IP or subsystem-level verification.

- Strong expertise in: SystemVerilogUVM Constrained-random verificationFunctional coverageCode coverageAssertions/SVARegression and failure debug

- Experience developing reusable UVM testbench components and verification infrastructure .

- Strong understanding of verification methodology, test planning, coverage closure, and sign-off.

- Experience with industry-standard simulators/debug environments such as Cadence Xcelium or equivalent.

- Ability to analyze complex specifications and translate requirements into effective verification scenarios.

- Strong debugging and problem-solving skills.
We’re doing work that matters. Help us solve what others can’t.