HW Verification Engineering Lead
- LocationPhoenix Building, Bangalore, India
- Work typeOn-site
- EmploymentFull-time
- Posted3 November 2026
- SourceSamsung's careers page (Workday)
Live checkFirst seen 6 days ago; still listed on Samsung's careers page 1 h ago.
At a glance
- Skills and toolsPython
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About the role
Position Summary
- Design, development & verification of H/W IP for camera, multimedia and display pipelines in smartphones
Role and Responsibilities
As the lead of IP Verification / Pre-Silicon Validation , you will head a team responsible for the verification of our next generation purpose specific custom HW IP . This critical role spans both in-house IP development as well as strategic evaluation, integration and validation of various other IP blocks. You will bridge the gap between technical execution and people mentorship , ensuring delivery, high quality, high performance and power – efficient hardware Ips that drive and differentiate our product line over competitors..
Skills and Qualifications
KEY RESPONSIBILITIES:
TECHNICAL EXECUTION AND DELIVERY:
- Oversee the end-to-end IP lifecycle and Advanced verification
- Ensure robust validation methods utilised to ensure zero-bug silicon
- Define and Implement best-in-class engineering practices, checklists and design flows to maximise efficiency
TECHNICAL COMPETENCIES:
- Verification / Emulation
- Understanding of digital design principles, algorithm, design and Architecture specifications
- Understanding of SystemC, C and Python Programming
- Design direction in terms of performance, gate count and power for various digital designs
- Proficient in System Verilog/UVM/OVM
- FPGA IP/Custom ASIC Prototyping and Validation
- Developing scalable Test benches in System Verilog and UVM
- Understanding of cameras / multimedia / display /NPU subsystems in detail
- Proven track record of integrating complex sub-systems (PCIe, USB, DDR, ARM/RISC-V Cores, MIPI etc)
- Design - knowledge in Verilog, Linting, (CDC) clock domain crossing, synthesis, Timing Analysis, Low Power Implementation (UPF/CPF, Clock Gating, Power Domain)
- Usage for AI Tool e.g., Claude for IP development enhancement, KPI exploration.
KEY LEADERSHIP TRAIT:
- People Developer
- Cross Functional Bridge
- Resource Optimiser
- Decisive Problem Solver
- Influencer and Navigator
DESIRED QUALIFICATION
Graduate / Post Graduate in Electrical / Electronic Engineering / VLSI Design / Microelectronics
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